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syam404's avatar
syam404
Icon for New Contributor rankNew Contributor
5 years ago
Solved

Error: No spd files are included in quartus project

1)While performing Generate Simulator Setup Script for IP it shows Error: No spd files are included in quartus project. So we are unable to generate .tcl file for simulation 2)I am using quartus pr...
  • RichardT_altera's avatar
    RichardT_altera
    5 years ago

    Hi @syam404

    May I know does my latest reply help?

    Do you have further questions in regards to this case?

    Best Regards,
    Richard Tan

    p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.

RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
5 years ago

Hi @syam404

1. Have you try to Generate HDL for your platform designer system? You will need to generate the files through platform designer.

2. You may use our simulator Modelsim Intel FPGA Edition (license required) or Modelsim Intel FPGA Starter Edition (no license required). https://fpgasoftware.intel.com/21.2/?edition=pro

3. Are you using the Intel IP? I would recommend to use HDL instead of block diagram to write your design as the design getting larger and complicated.

You may refer to the User Guide(UG) below to check the simulation flow.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20093.pdf

You may test out the design example in the UG to learn how the simulation works.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.