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signal 9 error
I am using Quartus Prime Pro 21.2 .While doing full compilation in fitter I got the error Error(20549): Current module quartus_fit was unexpectedly terminated by signal 9. This may be because some system resource has been exhausted, or quartus_fit performed an illegal operation. You can view system resource requirements on the System and Software Requirements page of the Intel FPGA website (https://fpgasoftware.intel.com/requirements/). I have to store 1056 values each 9 bits.I am using the device AGFB027R24C2E1V. How to resolve this error?Solved2.6KViews0likes1CommentRe: error: assigning to 'int *' from incompatible type 'void *' strICtLy_conFidEnTial[strICtlY_CoNfidEnT
- Old code : int *VERY_toP_SEcRET = stRicTlY_ConfiDeNtial(sizeof(int).. - New code : int *VERY_toP_SEcRET = (int*)stRicTlY_ConfiDeNtial(sizeof(int).. Thank you sir 6 errors got resolved one error is remained Regards, Syam6.2KViews0likes1Commentpolar IP frozen bits defining
Sir/madam, 1) In the example design of polar IP there is a polar5g_codec_parameter.txt, in that do we need to specify N frozen bits for every new parameters. 2)In that they are using different set of reliability sequence(frozen bits) for same code block length. Is it really necessary. If this is true it is really tedious to define every time this sequence. 3) Is there any possibility to store this frozen bits sequence and give it to the polar ip from outside without defining every time in polar5g_codec_parameter.txt . For information I am using Intel Quartus Prime Pro 21.2 edition. Regards, Syam Sundar694Views0likes1CommentRe: Error: No spd files are included in quartus project
Good Morning Sir, I am using Modelsim Intel FPGA Starter Edition only. In quartus prime 21.2 there is no RTL simulator like any other versions, so I have only one option to simulate that is by generating ip setup simulation script while doing this after compilation I am getting error like How could I remove this error please help me @RichardTanSY_Altera I have already referred the below UG still my problem not solved. And many other UGs and Intel FPGA videos I saw. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20093.pdf Regards, Syam Sundar( syamsundarmalla99@gmail.com)8.1KViews0likes2Comments