Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Error: Missing Source

Hi all, I have two schematics in Quartus II.

In schematic two, I have a design that has the following "output" line that I name "pwm_final".

(add http)

img25.imageshack.us/img25/8682/pic1mht.jpg

In schematic one (the main attached to the project file), I want to feed pwm_final into the block, but I receive an error that pwm_final is missing a source.

img818.imageshack.us/img818/8533/pic2n.jpg

Understandable, how do I get the two to "link"?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I couldnt see your images because it asked to log in so i am trying without seeing it.

    Missing source so from where your pwm_final is coming? that thing is missing in your design.so might be you havenot connected that singal to its source.

    Or for ex,if you have thought to feed signal though your logic that logic schematic is missing or if you want to assign only pin(which feeds input to pwm_final) then you havenot assigned it so signal is not able to recognise that from where it should take the input and feed to the design block.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    You should be able to copy the URL for the image, paste it into the address bar and view it.

    But what I was wondering is if I use the Orthogonal Node tool to produce a line going out of a counter in SpareDesign.bdf called "pwm_final", how do I make sure OtherDesign.bdf can use the output line "pwm_final"?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    if your pwm_signal is one bit then it should work,analysis code if it works properly and if u wonder about that line then connect directly from one block to another block.Directly in the sense,dnt cut the line.Only single line between blocks and try to figure out what is happening.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    All signals from the lower level schematic, that need to be connected to the upper entity must have input/output ports. Then they are exposed at the schematic symbol of the subdesign.