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KarelSterckx's avatar
KarelSterckx
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

Error in Timing Simulation Display

I am trying to run timing simulation in Questa Sim Intel Starter Edition (Quartus Prime Lite v22.1.1). After fitting, the compilation is correctly done and also the timing simulation is executed with...
  • KarelSterckx's avatar
    KarelSterckx
    3 years ago

    Thank you very much for this information. I will definitely look into it.

KarelSterckx's avatar
KarelSterckx
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

I forgot to mention that I am using the DE0-CV board and I am referring to the directory

C:/intelFPGA_lite/22.1std/questa_fse/intel/verilog/cyclonev