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I'm sure that the testbench set up the to meet the timing requirements.
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You can only say that if you've verified that the signals are generated from the testbench at a time compatible with what the timing report for that design states.
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If the timing requirements aren't met, the simulation should fail at any target FPGA,
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There is no basis for that statement. It is simply not true.
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but it succeeded when the target FPGA is CYCLONE or CYCLONEII and fails when the target FPGA is CYCLONEIII.
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That just says that the system to debug is the one with the Cyclone III in it.
You still need to verify that the setup time requirements being reported by Quartus for the Cyclone III design are being met by your testbench.
The next step is to verify that the outputs being sampled by your testbench (assuming that you're doing this) are being collected at times compatible with the clock to output delays being reported by Quartus for the Cyclone III design.
Until you've done this, there isn't much for anyone to help you with. If you have done this, then opening a case with Altera would likely be in order as well.
Kevin Jennings
Honored Contributor
