New Contributorerror ID 10170 HDL syntax error while using "typedef enum"
Hi ,
Im using Quartus Prime 19.1.0.670 (Cyclone10LP - 10CL120YF780I7G)
In my module im using "typedef enum ..." to evaluate my state machine current state :
//SM to Update SCAN MEM:
typedef
enum logic [3:0] //line(79)
{
SCAN_IF_IDLE = 4'h0,
SCAN_IF_CAPTURE_N = 4'h1,
SCAN_IF_CAPTURE_P = 4'h2,
SCAN_IF_START_N = 4'h3,
SCAN_IF_START_P = 4'h4,
SCAN_IF_EDT_UPDATE_N = 4'h5,
SCAN_IF_EDT_UPDATE_P = 4'h6,
SCAN_IF_CMD_N = 4'h7,
SCAN_IF_CMD_P = 4'h8,
SCAN_IF_SHIFT_N = 4'h9,
SCAN_IF_SHIFT_P = 4'hA,
SCAN_IF_LAST_N = 4'hB,
SCAN_IF_LAST_P = 4'hC,
SCAN_IF_DONE_N = 4'hD,
SCAN_IF_DONE_P = 4'hE
} t_S10_SCAN_IF_STATE; //line(96)
t_S10_SCAN_IF_STATE scan_if_state;
("scan_if_state" is the case statement in my SM)
got the bellow message :
Error (10170): Verilog HDL syntax error at svp_scan_if.sv(79) near text: "logic"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (10170): Verilog HDL syntax error at svp_scan_if.sv(96) near text: "}"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Is this Quartus version support this type of writing (sys verilog) ?
