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Altera_Forum
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15 years ago

Error generating ATLPLL for Cyclone III

Hi, I tried to to generate code for PLL with Megawizard plugin manager. I used multiply factor as 114 and division factor as 7. My input clock frequency is 16 MHz. When I compile the design, I ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

The PLL must find a least common multiple frequency for the VCO based on the input clock frequency and the mulitply/divide values (for all PLL outputs) that is in the range for the device (600 - 1300 MHz as pointed out by FvM).