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Altera_Forum
Honored Contributor
Honored ContributorError during generating simulation code in Qsys
I am using Quartus lite 16.1 on Ubuntu 16.10. I have a design that I can synthesize and can run on DE1-SoC board, and I am trying to do some simulation with my design. I am trying to generate te...
Altera_ForumHonored Contributor
Honored ContributorJust to make sure: you've exported the PLL input reference clock from the system, correct? This is necessary for Qsys to automatically add the clock BFM when generating the testbench system.
