Forum Discussion
sstrell
Super Contributor
6 years agoRapid recompile is only used/needed if you added/changed node usage in the .stp file after compiling the design. Otherwise, the .stp file should be compatible.
Even though it says to start RR, did you try just starting the logic analyzer running? If the file is compatible and you haven't made changes to the settings after compilation, it should work. I've seen weird status messages like that occur and the logic analyzer worked just fine.
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- SBasa56 years ago
New Contributor
Thanks for the answer.
My bad - I am modifying exisiting Cyclone SoC system. It is configured to boot from HPS side. After i have downloaded new FPGA config using JTAG: Linux rebooted the board and HPS bootloader overwritten my FPGA config.