Error: Can't run SignalTap II Logic Analyzer -- SignalTap II File is not compatible

I have ran into similar issue in Quartus Prime Lite 18.1.

I have created Signal Tap instance using: Tools->Signal Tap...

Compiled design. I can see sld_hub and sld_signaltap in hierarchy view (i can even locate it in chip planner after PAR)

Programmed device using sof.

In signal tap i have attached sof and it shows "compatible".

Signal Tap Logic Analyzer tool shows in red: "Start Rapid Recompile to continue".

Rapid recompile button is greyed out, using workaround: quartus_sh --flow recompile <proj_name>

Info (14904): Rapid Recompile skipped module Rapid Recompile Analysis & Synthesis because it is not required
Info (14904): Rapid Recompile skipped module Rapid Recompile Partition Merge because it is not required
Info (14904): Rapid Recompile skipped module Rapid Recompile Fitter (Place & Route) because it is not required
Info (14904): Rapid Recompile skipped module Rapid Recompile Assembler because it is not required
Info (293026): Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER
Info (14904): Rapid Recompile skipped module Rapid Recompile Timing Analysis because it is not required
Info (18207): Some modules have been skipped due to smart recompilation. You can turn off smart recompilation under Compilation Process Settings in the Settings dialog to fully recompile your design
Info (293000): Quartus Prime Rapid Recompile was successful. 0 errors, 0 warnings
Info (23030): Evaluation of Tcl script /opt/quartus/intelFPGA_lite/18.1/quartus/common/tcl/internal/qsh_flow.tcl was successful
Info: Quartus Prime Shell was successful. 0 errors, 0 warnings

Still nothing - cannot start my signaltap node.

Please help.