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14 years ago

Error: Cannot place I/O pin epcs_data_out with I/O standard 3.3-V LVCMOS in pin locat

Dears,

I encounted a error when I use EP4CE15E22I7N in QII 10.1.

Error: Cannot place I/O pin epcs_data_out with I/O standard 3.3-V LVCMOS in pin location 13 -- possible switch coupling with I/O pin epcs_clk_out in pin location 12.

qsf is attached.


#  --------------------------------------------------------------------------# 
# 
#  Copyright (C) 1991-2010 Altera Corporation
#  Your use of Altera Corporation's design tools, logic functions 
#  and other software and tools, and its AMPP partner logic 
#  functions, and any output files from any of the foregoing 
#  (including device programming or simulation files), and any 
#  associated documentation or information are expressly subject 
#  to the terms and conditions of the Altera Program License 
#  Subscription Agreement, Altera MegaCore Function License 
#  Agreement, or other applicable license agreement, including, 
#  without limitation, that your use is for the sole purpose of 
#  programming logic devices manufactured by Altera and sold by 
#  Altera or its authorized distributors.  Please refer to the 
#  applicable agreement for further details.
# 
#  --------------------------------------------------------------------------# 
# 
#  Quartus II
#  Version 10.1 Build 153 11/29/2010 SJ Full Version
#  Date created = 17:10:46  July 19, 2011
# 
#  --------------------------------------------------------------------------# 
# 
#  Notes:
# 
#  1) The default values for assignments are stored in the file:
# 		robost_v32_assignment_defaults.qdf
#     If this file doesn't exist, see file:
# 		assignment_defaults.qdf
# 
#  2) Altera recommends that you do not modify this file. This
#     file is updated automatically by the Quartus II software
#     and any changes you make may be lost or overwritten.
# 
#  --------------------------------------------------------------------------# 
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE15E22I7
set_global_assignment -name TOP_LEVEL_ENTITY robost_v32
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 10.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:10:46  JULY 19, 2011"
set_global_assignment -name LAST_QUARTUS_VERSION 10.1
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name VERILOG_FILE robost_v32.v
set_global_assignment -name QIP_FILE robost_cpu32.qip
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name QIP_FILE pll_1.qip
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name MISC_FILE "H:/25i-r/fpga_software/25i_Robost/r_v32_25i/robost_v32.dpf"
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "Custom Verilog HDL"
set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR timing/custom -section_id eda_timing_analysis
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_timing_analysis
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_timing_analysis
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to epcs_clk_out
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to epcs_data_out
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_location_assignment PIN_54 -to fpga_clk
set_location_assignment PIN_55 -to mcu_nrst
set_location_assignment PIN_12 -to epcs_clk_out
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_location_assignment PIN_13 -to epcs_data_out
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

How to solve it?
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