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Altera_Forum
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11 years ago

Error at Analysis and Synthesis step in Quartus 14.1 - (generic_pll primitive )

Hi, when i am running my design in quartus 14.1 it is throwing error as - Error (129037): Output port OUTCLK on atom "vip_example:sys|vip_example_mem_if_ddr3_emif_0:mem_if_ddr3_emif_0|vip_...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi,

I have additionally created a small design and checked that the issue is device independent (in Quartus 14.1).

As far as i have gone through, the issue is with "ddr3 SDRAM controller with Uniphy". you may check at your end in order to confirm.