Error 19724: not enough LAB's for clock region

Hi Ven,

Thanks for answering, but this is what I found myself already. The issue is, I cannot find how to use the various commands.

Let me respond to your suggestions

1/ Go to Assignments > Assignment Editor, then in Assignment name column search for Clock Region and fill in other column details.

When I open Assignment editor, I get the following:

So,. There is not a “clock region” mentioned.

If I enter “clock Region” under “assignment name”, I get “yes” under enabled, in Entity “altera_eth_top”. What next?

And if it would have been there, what should I have filled in?

2/ Open the QSF file and add the command you mentioned above to the QSF file.

As I mentioned, I do not know how to use those commands in the QSF file:

1. I used set_global_assignment -name GLOBAL_PLACEMENT_EFFORT "HIGH EFFORT", without succes
2. quartus does not accept:set_global_assignment -name GLOBAL_PLACEMENT_EFFORT "OPTIMIZE FOR HIGH UTILIZATION", (Quartus removes it from qsf file)
3. I cannot find the syntax and parameters in set_instance_assignment -name CLOCK_REGION -to <to> -entity <entity name><value>
   I understand the syntax is something like -to “SX0 SY0 SX100 SY 100” (how to find the correct values?), and what are the values and syntax for <entity name> (is that “altera_eth_top”? or is that one of the entities below that?), and what is the value and syntax for <value>? I have no clue, and I cannot find it in a manual or example
4. I cannot find the syntax and parameters in set_instance_assignment -name CLOCK_REGION -from <from> -to <to> -entity<entity name> <value>,
   I understand the syntax is something like -to “SX0 SY0 SX100 SY 100” (how to find the correct values?), and what are the values and syntax for <entity name> (is that “altera_eth_top”? or is that one of the entities below that?), and what is the value and syntax for <value>? I have no clue, and I cannot find it in a manual or example
5. In the *.fit.rpt and *.fit.place.rpt report you can find:

Error (19724): Fitter requires 646 LABs for clock region in locations from lower-left (13, 32) to upper-right (37, 58), but only 621 LABs are available exclusively for that region

Info (19797): The following node of the above-mentioned region failed to pack: "dut_inst|CHANNEL[0].wrapper_lpi|locklink_topIC|ic_b66_decode|Decoder_9~16 "dut_inst|CHANNEL[0].wrapper_lpi|locklink_topIC|ic_b66_decode|i30167~0" "dut_inst|CHANNEL[1].wrapper_lpi|locklink_topIC|b66_encode_ic|b66_enc_istore_ip|s_istore_fifo_cw[5].cw_lpi_stop" "dut_inst|CHANNEL[1].wrapper_lpi|locklink_topIC|b66_encode_ic|b66_enc_istore_ip|Select_1224~0" "dut_inst|CHANNEL[1].wrapper_lpi|locklink_topIC|ic_b66_decode|fsm2dpp_data[36]" Error (170025):

Fitter requires that more entities of type LAB be placed in a region than are available in the region File: C:/Users/piete/OneDrive/CO/CO_22_02/simulation/models/140_rx_stsp.vhd Line: 65

Error (170026): Region "lower-left" corner: X13_Y32; Region "upper-right" corner: X37_Y58

Info (170028): Region dimensions determined based on intersection of the following constraints: Promoted Clock Region

Error (170029): The following resources need to be used in this region

Error (18170): Fitter needs to use 646 out of 621 entities of type LAB in this region

Info (170036): The following sample cells belong to the region being placed.

Info (170000): Node "dut_inst|CHANNEL[0].wrapper_lpi|locklink_topIC|ic_stsp|barrel_i[16].data64[53]" File: C:/Users/piete/OneDrive/CO/CO_22_02/simulation/models/140_rx_stsp.vhd Line: 65

Info (170000): Node "dut_inst|CHANNEL[0].wrapper_lpi|locklink_topIC|ic_stsp|barrel_i[16].data64[12]" File: C:/Users/piete/OneDrive/CO/CO_22_02/simulation/models/140_rx_stsp.vhd Line: 65

Info (170000): Node "dut_inst|CHANNEL[0].wrapper_lpi|locklink_topIC|ic_stsp|barrel_i[16].data64[44]" File: C:/Users/piete/OneDrive/CO/CO_22_02/simulation/models/140_rx_stsp.vhd Line: 65

Info (170000): Node "dut_inst|CHANNEL[0].wrapper_lpi|locklink_topIC|ic_stsp|barrel_i[30].data64[44]" File: C:/Users/piete/OneDrive/CO/CO_22_02/simulation/models/140_rx_stsp.vhd Line: 65

Info (170000): Node "dut_inst|CHANNEL[0].wrapper_lpi|locklink_topIC|ic_stsp|barrel_i[16].data64[41]" File: C:/Users/piete/OneDrive/CO/CO_22_02/simulation/models/140_rx_stsp.vhd Line: 65

Info (170000): Node "dut_inst|CHANNEL[0].wrapper_lpi|locklink_topIC|ic_stsp|barrel_i[20].data64[41]" File: C:/Users/piete/OneDrive/CO/CO_22_02/simulation/models/140_rx_stsp.vhd Line: 65

Info (170000): Node "dut_inst|CHANNEL[0].wrapper_lpi|locklink_topIC|ic_stsp|barrel_i[16].data64[10]" File: C:/Users/piete/OneDrive/CO/CO_22_02/simulation/models/140_rx_stsp.vhd Line: 65

Info (170000): Node "dut_inst|CHANNEL[0].wrapper_lpi|locklink_topIC|ic_stsp|barrel_i[16].data64[25]" File: C:/Users/piete/OneDrive/CO/CO_22_02/simulation/models/140_rx_stsp.vhd Line: 65

Info (170000): Node "dut_inst|CHANNEL[0].wrapper_lpi|locklink_topIC|ic_stsp|barrel_i[20].data64[25]" File: C:/Users/piete/OneDrive/CO/CO_22_02/simulation/models/140_rx_stsp.vhd Line: 65

Info (170000): Node "dut_inst|CHANNEL[0].wrapper_lpi|locklink_topIC|ic_stsp|barrel_i[16].data64[26]" File: C:/Users/piete/OneDrive/CO/CO_22_02/simulation/models/140_rx_stsp.vhd Line: 65

(line 65 is a an array with 32 records, each with a vector data64 [63:0], sh [1:0] and a Boolean)

3/ Lastly, you may check out the following links to learn more about the clock region.

I have read that, but it does not explain how to repair this issue.

4/ Forum on solving the Error19724:

That is the link I gave to you, where the above suggestions under 2/ are given, but without guidance on how to use them

So, I hope you can give me more precise and elaborated help.

Thanks for your support.

Regards, Pieter

Summary says: (it looks as if there is plenty of room)….

Fitter Status : Failed - Wed Aug 24 12:38:27 2022

Quartus Prime Version : 20.2.0 Build 50 06/11/2020 SC Pro Edition

Revision Name : altera_eth_top

Top-level Entity Name : altera_eth_top

Family : Cyclone 10 GX

Device : 10CX220YF780E5G

Timing Models : Final

Power Models : Final

Device Status : Final

Total registers : 54903

Total pins : 29 / 340 ( 9 % )

Total virtual pins : 97

Total block memory bits : 292,672 / 12,021,760 ( 2 % )

Total RAM Blocks : 74 / 587 ( 13 % )

Total DSP Blocks : 1 / 192 ( < 1 % )

Total HSSI RX channels : 2 / 12 ( 17 % )

Total HSSI TX channels : 2 / 12 ( 17 % )

Total PLLs : 4 / 30 ( 13 % )