Forum Discussion
AminT_Intel
Regular Contributor
4 years agoHello,
I am sorry that you are facing this problem. I will try my best to help you.
I believe these fitter errors are due to the invalid reconfiguration clock pin location assignments in the Intel Stratix 10 Hard IP for PCI Express MX H-Tile ES1 FPGA Devkit Design Example. Please go through this workaround: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/ip/2018/error-175020---the-fitter-cannot-place-logic-pin-that-is-part-of.html
Thank you.
- AminT_Intel4 years ago
Regular Contributor
Hello,
Is all of your questions addressed? I will close this case in 3 days if there is no response from you.
Thanks.