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WGao1's avatar
WGao1
Icon for New Contributor rankNew Contributor
7 years ago

Error (175001) When Compile CvP Revision for CvP Update Mode (Cyclone V GX)

I followed the Design Steps for CvP Update Mode descripted in the Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide. The base revision is compiled successfully. Howe...
JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

It looks like you are designing your design with more than the available clock routing on that particular clock source. I would recommend you to move some of the clock to another clock source.

If you need help on resolving the issue then I will need to have your design in order to investigate the root cause.