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Altera_Forum's avatar
Altera_Forum
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10 years ago

Error (169102): I/O Bank "5" of VCCIO assignment 1.8V is out of range - please use on

Device: Arria II GX

VCCIO set to 2.5V in Device and Pin options

All pins are assigned to 2.5V input or output.

How to fix below IO analysis error?

Error (169102): I/O Bank "5" of VCCIO assignment 1.8V is out of range - please use one of the following I/O banks:

Info (169103): I/O Bank "QL1"

Info (169103): I/O Bank "QL0"

Info (169103): I/O Bank "3C"

Info (169103): I/O Bank "3A"

Info (169103): I/O Bank "4A"

Info (169103): I/O Bank "5A"

Info (169103): I/O Bank "6A"

Info (169103): I/O Bank "7A"

Info (169103): I/O Bank "8A"

Info (169103): I/O Bank "8C"

Error (169102): I/O Bank "5" of VCCIO assignment 1.8V is out of range - please use one of the following I/O banks:

Info (169103): I/O Bank "QL1"

Info (169103): I/O Bank "QL0"

Info (169103): I/O Bank "3C"

Info (169103): I/O Bank "3A"

Info (169103): I/O Bank "4A"

Info (169103): I/O Bank "5A"

Info (169103): I/O Bank "6A"

Info (169103): I/O Bank "7A"

Info (169103): I/O Bank "8A"

Info (169103): I/O Bank "8C"

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    It sounds like you have something set to use a 1.8V iostandard. Can you forward your qsf file and what version of quartus you are using?

    Regards,

    Pete
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Thanks for the response.

    Below is the .qsf file. The design was in Cyclone II, and I changed the device to Arria II GX (to fix timing issues). While doing that, I had to reassign IOs, and encountered aforementioned VCCIO issue. The .qsf is not updated to reflect this, not sure why.

    This is on Quartus 11.1

    set_global_assignment -name FAMILY "Cyclone II"

    set_global_assignment -name DEVICE EP2C5F256C6

    set_global_assignment -name TOP_LEVEL_ENTITY pipemult

    set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0

    set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:10:20 JANUARY 11, 2006"

    set_global_assignment -name LAST_QUARTUS_VERSION 6.0

    set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA

    set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256

    set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST

    set_global_assignment -name VERILOG_FILE mult.v

    set_global_assignment -name VHDL_FILE ram.vhd

    set_global_assignment -name BDF_FILE pipemult.bdf