Forum Discussion
Deshi_Intel
Regular Contributor
4 years agoHi,
From the diagram that you drew, likely this is due to resource sharing issue.
- You are using same CDR_refclk source to clock 2 NativePHY IP where by one transceiver bank only contains 6 channel.
- If you are using CMU PLL, then it will eat up extra transceiver channel as well.
- I am guessing once you remove the second NativePHY design then it free up some transceiver channel resource, that's why no more error
I can't analyze the issue further unless you can share with me your design QAR file. I need to cross check your NativePHY IP setting vs your transceiver pin setting.
Anyway, my suspect is due to insufficient transceiver channel resource sharing issue that caused the error
Thanks.
Regards,
dlim
- yy14 years ago
New Contributor
Hi Dlim,
Thanks for your explain.
And what's the QAR file mean ? How can I get this file?
Thanks
Jamie