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Altera_Forum
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11 years ago

ERROR 129001 Input port DINFIFORX .... is not legally connected

Hi everybody,

this is my first post .... so bear with me.

I am having some compilation issues in Quartus. I tried googling and found no answers. I tried posing a service request but i cant.

I am using 5CEBA2F17C6 cyclone VE. During my compilation i get this errors

error (129001): input port dinfiforx on atom "lvds_control:lvds_init|lvds_sync:lvds_sync_init_top|lvds_deser_cy5:lvds_deser_inst1|altlvds_rx:altlvds_rx_component|lvds_deser_cy5_lvds_rx1:auto_generated|sd1", which is a cyclonev_ir_fifo_userdes primitive, is not legally connected and/or configured info (129003): input port dinfiforx[0] is driven by a constant signal, but the compiler expects this input port to be connected to a real signal

error (129001): input port dinfiforx on atom "lvds_control:lvds_init|lvds_sync:lvds_sync_init_bottom|lvds_deser_cy5:lvds_deser_inst1|altlvds_rx:altlvds_rx_component|lvds_deser_cy5_lvds_rx1:auto_generated|sd5", which is a cyclonev_ir_fifo_userdes primitive, is not legally connected and/or configured

info (129003): input port dinfiforx[0] is driven by a constant signal, but the compiler expects this input port to be connected to a real signal

can some one tell me what this is and how to fix it.

Thank you

Regards

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Hello,

    Just in case anybody would stumble upon this problem: you cannot connect internal signals or constants to the inputs of the ALTLVDS_RX megafunction; the pins must be real LVDS pins of the FPGA.