Error (12252): Border: 2020.05.20.09:07:13 Error: seq: Error during execution of "{C:/intelfpga_lite/19.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2 stderr.txt": child process exited abnormally

Question

I'm regenerating a hps system with the Platform Designer and receive a couple of errors during execution of script generate_hps_sdram.tcl

This is the situation when I click Tool>>tcl scripts..>>hps_sdram_p0_pin_assignments.tcl>>run

Error:Info: *******************************************************************

Error:Info: Running Quartus Prime Timing Analyzer

Error: Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition

Error: Info: Your use of Intel Corporation's design tools, logic functions

Error: Info: and other software and tools, and any partner logic

Error: Info: functions, and any output files from any of the foregoing

Error: Info: (including device programming or simulation files), and any

Error: Info: associated documentation or information are expressly subject

Error: Info: to the terms and conditions of the Intel Program License

Error: Info: Subscription Agreement, the Intel Quartus Prime License Agreement,

Error: Info: the Intel FPGA IP License Agreement, or other applicable license

Error: Info: agreement, including, without limitation, that your use is for

Error: Info: the sole purpose of programming logic devices manufactured by

Error: Info: Intel and sold by Intel or its authorized distributors. Please

Error: Info: refer to the applicable agreement for further details, at

Error: Info: https://fpgasoftware.intel.com/eula.

Error: Info: Processing started: Wed May 20 09:13:14 2020

Error:Info: Command: quartus_sta -t C:/intelFPGA_lite/19.1/my_first_hps-fpga_mh/fpga-rtl/soc_system/synthesis/submodules/hps_sdram_p0_pin_assignments.tcl soc_system

Error:Info: Quartus(args): soc_system

Error:Warning (125092): Tcl Script File DDR3_sdram.qip not found

Error: Info (125063): set_global_assignment -name QIP_FILE DDR3_sdram.qip

Error:Warning (125092): Tcl Script File DDR3_sdram.sip not found

Error: Info (125063): set_global_assignment -name SIP_FILE DDR3_sdram.sip

Error:Warning (125092): Tcl Script File ddr3.qip not found

Error: Info (125063): set_global_assignment -name QIP_FILE ddr3.qip

Error:Warning (125092): Tcl Script File ddr3.sip not found

Error: Info (125063): set_global_assignment -name SIP_FILE ddr3.sip

Error:Info: Cleaning up stale assignments...

Error:Error (23031): Evaluation of Tcl script C:/intelFPGA_lite/19.1/my_first_hps-fpga_mh/fpga-rtl/soc_system/synthesis/submodules/hps_sdram_p0_pin_assignments.tcl unsuccessful

Error:Error: Quartus Prime Timing Analyzer was unsuccessful. 1 error, 4 warnings

Error: Error: Peak virtual memory: 4630 megabytes

Error: Error: Processing ended: Wed May 20 09:13:16 2020

Error: Error: Elapsed time: 00:00:02

Error: Error: Total CPU time (on all processors): 00:00:02

Error:------------------------------------------------

Error:ERROR: Can't run the Timing Analyzer (quartus_sta) -- Partition Merge (quartus_cdb --merge) failed or was not run. Run the Partition Merge (quartus_cdb --merge) successfully before running the Timing Analyzer (create_timing_netlist -post_map).

Error: while executing

Error:"create_timing_netlist -post_map"

Error: invoked from within

Error:"if { ! [ timing_netlist_exist ] } {

Error: create_timing_netlist -post_map

Error:}"

Error: (file "C:/intelFPGA_lite/19.1/my_first_hps-fpga_mh/fpga-rtl/soc_system/synthesis/submodules/hps_sdram_p0_pin_assignments.tcl" line 174)

Error:------------------------------------------------

Error: while executing

Error:"exec $cmd -t [ info script ] $project_name "

Error: invoked from within

Error:"if { ![info exists quartus(nameofexecutable)] || ($quartus(nameofexecutable) != "quartus_sta" && $quartus(nameofexecutable) != "quartus_map") } {

Error: pos..."

Error: (file "C:/intelFPGA_lite/19.1/my_first_hps-fpga_mh/fpga-rtl/soc_system/synthesis/submodules/hps_sdram_p0_pin_assignments.tcl" line 110)

Error: invoked from within

Error:"_source C:/intelFPGA_lite/19.1/my_first_hps-fpga_mh/fpga-rtl/soc_system/synthesis/submodules/hps_sdram_p0_pin_assignments.tcl"

Error: ("uplevel" body line 1)

Error: invoked from within

Error:"uplevel 1 $cmd "

Error: (procedure "source" line 5)

Error: invoked from within

Error:"source "C:/intelFPGA_lite/19.1/my_first_hps-fpga_mh/fpga-rtl/soc_system/synthesis/submodules/hps_sdram_p0_pin_assignments.tcl""

And this is the situation when I click Procssing>>start complication

Error (12252): Border: 2020.05.20.09:07:13 Error: seq: Error during execution of "{C:/intelfpga_lite/19.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally

Error (12252): Border: 2020.05.20.09:07:13 Error: seq: Execution of command "{C:/intelfpga_lite/19.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed

Error (12252): Border: 2020.05.20.09:07:13 Error: seq: child process exited abnormally

Error (12252): Border: 2020.05.20.09:07:14 Error: seq: add_fileset_file: No such file D:/Temp/alt8402_6616470643549882170.dir/0004_seq_gen/hps_AC_ROM.hex

Error (12252): Border: while executing

Error (12252): Border: "add_fileset_file $file_name [::alt_mem_if::util::hwtcl_utils::get_file_type $file_name 0] PATH $file_pathname"

Error (12252): Border: ("foreach" body line 4)