Error (12014): Net "a", which fans out to "a", cannot be assigned more than one value

I'm designing a relatively simple circuit. Using two 4 to 2 encoders to realize an 8 to 3 encoder. Only been learning VHDL the last month. I don't know what this error means. I've done similar circuits without error so I'm not sure what the difference is.

Error (12014): Net "a", which fans out to "a", cannot be assigned more than one value

Error (12015): Net is fed by "ENCODER4X2:M1|a"

Error (12015): Net is fed by "ENCODER4X2:M2|a"

Error (12014): Net "b", which fans out to "b", cannot be assigned more than one value

Error (12015): Net is fed by "ENCODER4X2:M1|b"

Error (12015): Net is fed by "ENCODER4X2:M2|b"

top design:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

Entity ENCODER8X3 IS

PORT (i0, i1, i2, i3, i4, i5, i6, i7 : IN STD_LOGIC;

error 12014 -> a, b, c, d : OUT STD_LOGIC);

END ENCODER8X3;

ARCHITECTURE STRUCT OF ENCODER8X3 IS

signal w1 : std_LOGIC;

COMPONENT ENCODER4X2

PORT (i0, i1, i2, i3 : IN STD_LOGIC;

a, b, c : OUT STD_LOGIC);

END COMPONENT;

BEGIN

w1 <= not (i0 OR i2 OR i4 OR i6);

M1: ENCODER4X2 PORT MAP (i0, i2, i4, i6, a, b, w1);

M2: ENCODER4X2 PORT MAP (i1, i3, i5, i7, a, b, d);

END STRUCT;

slave device:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY ENCODER4X2 IS

PORT (i0, i1, i2, i3 : IN STD_LOGIC;

&#8203;error 12015 -> a, b, c : OUT STD_LOGIC);

END ENCODER4X2;

ARCHITECTURE STRUCT OF ENCODER4X2 IS

BEGIN

a <= i3 OR i2;

b <= (i1 AND (NOT i2)) OR i3;

c <= i0 OR i1 OR i2 OR i3;

END STRUCT;

It's probably some stupid mistake that I'm overlooking. I hope so. Any help is appreciated.