error 10818 with simple VHDL construct under Quartus v 12.1 build 177

I just verified, that Quartus is also complaining about the original Verilog code, which was expectable.

In fact you can change it to regular synthesizable Verilog by exchanging a few lines, corresponding to the VHDL version shown in post# 5 and# 6. In so far it's completely misterious why the author used the starnge construct.

Regarding sensitivity lists, in my understanding, they have been introduced to reduce the effort of a simulator that has to interprete the code. Using process(all) in VHDL (or always @* in Verilog) means that the simulator has to compute all expressions for each delta cycle, but also avoids all possible simulation mismatches related to sensitivity lists.

You can argue that sensitivity lists are ignored in synthesis anyway, so if you are only simulating synthesizable code, or not simulating it at all, you can use process(all) without changing anything.

P.S. The corrected Verilog code

always @(posedge clk or posedge rst )
  if (rst) begin
    m_wr_pnt<=0;
    write_cnt<=0;
    new_bw <=0; 
    read_cnt<=0;
   end
  else
  begin
   new_bw <=0;    
   if (we_m) begin    
    if (free_bd >0) begin
      write_cnt <=write_cnt+1;
      m_wr_pnt<=m_wr_pnt+1;
      if (!write_cnt) begin      //First write indicate source buffer addr (2x16)
        bd_mem<=dat_in_m;             
      end
      else begin        //Second write indicate SD card block addr (2x16)
        bd_mem<=dat_in_m;
        new_bw <=write_cnt;      //Second 16 bytes writen, complete BD
      end
     end
  end   
end