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Well - before VHDL2008 emerged I was, or course, using the explicit sensitivity list. But blame it on my stupidity, but it's been certainly more then once, when simulation result was different from synthesized circuit operation
due to omitting some arguments from the sensitivity list (which synthesis tools ignore).
Thus nowdays I prefer to use the form that is consistent between simulation and synthesis.
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I would argue that this is a bad approach for a clocked process. In the case of a clocked process, just list the clock and reset. For a combinatorial process, sure use all to save yourself forgetting a signal. But even then, Quartus will warn you if you have missed a signal in the sensitivity list of a process, so just make sure to read the warning messages. Similarly, your Modelsim testbench should fail if you've forgotten a signal in the sensitivity list, and your testbench provides full code coverage.
Bottom-line, if you have a good test and verification policy in place, you don't need to be "lazy" and use process(all).
These are just my preferences ...
Cheers,
Dave
Honored Contributor
