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Your process line should be process(clk,rst). Sure, all works, but it does not provide your "intent" for the logic. Explicitly indicating you wanted the process only to be sensitive to clock and reset helps the next person maintaining your code understand it better.
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Well - before VHDL2008 emerged I was, or course, using the explicit sensitivity list. But blame it on my stupidity, but it's been certainly more then once, when simulation result was different from synthesized circuit operation
due to omitting some arguments from the sensitivity list (which synthesis tools ignore).
Thus nowdays I prefer to use the form that is consistent between simulation and synthesis.
Honored Contributor
