Altera_Forum
Honored Contributor
Honored Contributorerror 10818 with simple VHDL construct under Quartus v 12.1 build 177
I've stumbled on a rather simplistic code, that is not synthesizable. I wonder why (VHDL 2008 mode): library IEEE;
use IEEE.std_logic_1164.all;
entity reset_test is
port (
clk,rst,ena :...
