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Altera_Forum
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12 years ago

error 10818 with simple VHDL construct under Quartus v 12.1 build 177

I've stumbled on a rather simplistic code, that is not synthesizable. I wonder why (VHDL 2008 mode): library IEEE; use IEEE.std_logic_1164.all; entity reset_test is port ( clk,rst,ena :...
Altera_Forum's avatar
Altera_Forum
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12 years ago

As a first comment, the unconditional assignment "new_bw <=0" in the quoted Verilog code is not corresponding to the standard for synthesizable Verilog (IEEE Std 1364.1). I'm not sure, if it will be accepted by all tools and achieves consistency between simulation and hardware behaviour. You can hardly translate bad Verilog code to synthesizable VHDL without some rework.

To resolve the bad code issue, you have to analyze the original code for the usage of the reg variable new_bw in other places and determine the intended behaviour. The problem can't be clarified by only looking at the quoted always block.