error 10818 with simple VHDL construct under Quartus v 12.1 build 177

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Thus the question is:

What is the proper pattern to assign some output signal in the process on clock edge, but only till next clock and only if some (maybe complex) condition is met, and else set it do default value?

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you can use default statement:

if reset ...

elsif rising_edge(clk) then

data <= '0';

if condition1 then

data <= '1';

end if;

end if;

condition1 will be checked at every clock edge and if not true then '0' is assigned on data