error 10818 with simple VHDL construct under Quartus v 12.1 build 177

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What is the proper pattern to assign some output signal in the process on clock edge, but only till next clock and only if some (maybe complex) condition is met, and else set it do default value?

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Hmm, I normally only use that construct in a combinatorial process. I'd expect it to be something like:

D1: process (all)
begin
  if rst then
     result <='0';
  elsif rising_edge(clk) then
     -- Default
     result <= '0';
     -- Override
     if (some other condition) then
         result <= ena;
     end if;
  end if;
end process;

Cheers,

Dave