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Altera_Forum's avatar
Altera_Forum
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12 years ago

error 10818 with simple VHDL construct under Quartus v 12.1 build 177

I've stumbled on a rather simplistic code, that is not synthesizable. I wonder why (VHDL 2008 mode): library IEEE; use IEEE.std_logic_1164.all; entity reset_test is port ( clk,rst,ena :...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Your problem in converting the code to VHDL is that Verilog has blocking and non-blocking assignment operators. Download the SystemVerilog spec here:

http://standards.ieee.org/getieee/1800/download/1800-2012.pdf

and look at the section on "Assignment Statements".

My SystemVerilog skills are limited, so I'll leave it to someone else to provide insight as to what is occurring.

Cheers,

Dave