error 10818 with simple VHDL construct under Quartus v 12.1 build 177

Ok, thank you very much Dave for the insight. Here is the full story of this construct.

While working on sdc_controller from OpenCores (SD card controller) I was getting Error 10818. Never seen it with my own code - I've been indoctrinated well to avoid this :) It seems, that authors of that code were using Actel tools, that should be comfortable with the above coding style (which I still don't like). For example one of the fragments looks like this:

always @(posedge clk or posedge rst )
begin
   new_bw <=0;    
  if (rst) begin
    m_wr_pnt<=0;
    write_cnt<=0;
    new_bw <=0; 
    read_cnt<=0;
   end
  else if (we_m) begin    
    if (free_bd >0) begin
      write_cnt <=write_cnt+1;
      m_wr_pnt<=m_wr_pnt+1;
      if (!write_cnt) begin      //First write indicate source buffer addr (2x16)
        bd_mem<=dat_in_m;             
      end
      else begin        //Second write indicate SD card block addr (2x16)
        bd_mem<=dat_in_m;
        new_bw <=write_cnt;      //Second 16 bytes writen, complete BD
      end
     end
  end   
end

Now, if I want to take out assignment new_bw<=0 before the 'if' assignment, I need to put 'else new_bw<='0'' to several places.

And this is prone to error. And if I miss one, the D-trigger will be inferred and the design will not operate as intended.

Thus the question is:

what is the proper pattern to assign some output signal in the process on clock edge, but only till next clock and only if some (maybe complex) condition is met, and else set it do default value?