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Altera_Forum's avatar
Altera_Forum
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12 years ago

error 10818 with simple VHDL construct under Quartus v 12.1 build 177

I've stumbled on a rather simplistic code, that is not synthesizable. I wonder why (VHDL 2008 mode): library IEEE; use IEEE.std_logic_1164.all; entity reset_test is port ( clk,rst,ena :...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Because having the line:

result <= '0';

before the if statement does not match the "pattern" used to infer a register.

Drop that line and it'll synthesize fine.

Your process line should be process(clk,rst). Sure, all works, but it does not provide your "intent" for the logic. Explicitly indicating you wanted the process only to be sensitive to clock and reset helps the next person maintaining your code understand it better.

Cheers,

Dave