Error (10818): (does not hold its value outside the clock edge)

I am having the same problem too - Error 10818 (does not hold its value outside the clock edge) and 10822 (couldn't implement registers for assignment on this clock edge) but i cant understand what changes do i need to do.

I am trying to build a Counter that count the time user successfully catches a number 8.

If it is, then a logic '1' will be sent out and a signal will record the times of success events and sent out too.

I have another question is "can i use rising_edge to detect any change of logic value for any time of signal ? std_logic / unsigned / integer .. etc ....

Here is the code

--- Quote Start ---

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

entity catch is

port (

PUSH : in std_logic;

COMP : in unsigned(3 downto 0);

RST : in std_logic;

INC_FREQ : out integer range 1 to 10;

SCORE_COUNT : out std_logic

);

end catch;

architecture catch_arch of catch is

signal var_INC_FreQ : integer range 1 to 10;

begin

process (RST,PUSH,COMP)

begin

if RST = '0' then

var_INC_FREQ <= 1;

elsif rising_edge(PUSH) then

if COMP = 8 then

SCORE_COUNT <= '1';

var_INC_FREQ <= var_INC_FREQ + 1;

end if;

else

SCORE_COUNT <= '0';

end if;

end process;

INC_FREQ <= var_INC_FREQ;

end catch_arch;

--- Quote End ---

Thanks alot !