Forum Discussion
Altera_Forum
Honored Contributor
16 years agoThe recommended way of writing a process that can be synthesized is the following:
process(clock,reset)
begin
if (reset = '1') then
-- reset conditions
elsif (rising_edge(clock)) then
-- clocked operations
end if;
end process;The reset part is optional, but recommended. I think that in your case the synthesizer is confused by your first if in the process and doesn't know what to do with it. It isn't a reset condition, and you are assigning signal values outside of a clock edge. You should change your first part as a real reset condition, or scrap it and give correct initial values to q_int, q1_int and q2_int. You could also keep only one counter and assign its value +1 or +2 to the correct output. You shouldn't need to use the L and H values if you do everything inside the clocked part of the process.