Honored Contributor
Honored ContributorSome of your constructs can never work in logic hardwire design, e.g. operating a counter without an edge sensitive condition. (in the second part of process_button1_handler).
What update rate do you expect for the counter? Where should it come from? You can possibly have both ansynchronous and synchronous set for a register value like button1_go. But to be recognized as an asynchronous preset, the condition must take precedence over the synchronous action, but you have reversed the precedence. --- Quote Start --- In addition, does QII have a predefined TRUE and FALSE? --- Quote End --- VHDL has it for the boolean data type.
