keegandent
New Contributor
2 years agoError (10742): Verilog HDL error: constant expression cannot contain a hierarchical identifier
It seems this issue may not have been resolved, at least not in a way that applies to SystemVerilog `interface` objects.
This is a toy example, but I can provide Quartus project upon request. I am using 23.1.1std.
The following code, given a defined interface with a parameter DATA_WIDTH_BYTES...
module foo ( input logic clk, input logic arstn, axis.s s_axis, axis.m m_axis ); localparam DATA_WIDTH = s_axis.DATA_WIDTH_BYTES * 8; ... endmodule
...will produce the following error:
Error (10742): Verilog HDL error at foo.sv(7): constant expression cannot contain a hierarchical identifier
This doesn't seem to violate any SystemVerilog language standards; indeed Verilator and Vivado synthesize the design without complaint.