Hi, i have problems with my vhdl code. This is the code: LIBRARY IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use ieee.numeric_std.all; ENTITY brake_var IS port ( clk : in std_logic; reset : in std_logic; chip_select : in std_logic; writedata : in std_logic_vector (31 downto 0); write_n : in std_logic; address : in std_logic; readdata : out std_logic_vector (31 downto 0); out_port1 : out std_logic_vector (7 downto 0); out_port2 : out std_logic_vector (7 downto 0)); END brake_var; ARCHITECTURE brake_system OF brake_var IS signal D : unsigned (31 downto 0); -- distance d'arrÃªt signal v : unsigned (31 downto 0); -- vitesse du vÃ©hicule signal Dmax : unsigned (31 downto 0); -- vitesse max (danger) signal tb : std_logic; signal brake : std_logic; BEGIN readdata <= std_logic_vector(D) when address = '0' else std_logic_vector(v); registers: PROCESS (clk, reset) BEGIN if reset = '0' then D <= (others =>'0'); v <= (others =>'0'); elsif clk'event and clk = '1' then if chip_select ='1' and write_n = '0' then if address = '0' then D (31 downto 0) <= unsigned(writedata (31 downto 0)); else v (15 downto 0) <= unsigned(writedata (15 downto 0)); end if; end if; end if; END PROCESS; distance : PROCESS (clk,reset) begin if reset = '0' then D <= (others =>'0'); elsif clk'event and clk='1' then D(31 downto 0) <= (v(15 downto 0)*3)/10 + (v(15 downto 0)*v(15 downto 0))/100; else D <= (others =>'0'); end if; END PROCESS; tableau_de_bord : PROCESS (clk,reset) begin if reset = '0' then tb <= '0'; elsif clk'event and clk='1' then tb <= '0' when D < Dmax else '1' when D > Dmax; end if; end process; frein : PROCESS (clk,reset) begin if reset = '0' then brake <= '0'; elsif clk'event and clk='1' then brake <= '0' when tb = '0' else '1' when tb ='1';-- freinage end if; END PROCESS; out_port1 <= (others=> tb); out_port2 <= (others=> brake); END brake_system ; And the error : Error (10500): VHDL syntax error at ppp.vhd(61) near text "when"; expecting ";" Error (10500): VHDL syntax error at ppp.vhd(71) near text "when"; expecting ";" Error: Quartus II 32-bit Analyze Current File was unsuccessful. 2 errors, 0 warnings Error: Peak virtual memory: 329 megabytes Error: Processing ended: Sun May 25 19:34:03 2014 Error: Elapsed time: 00:00:03 Error: Total CPU time (on all processors): 00:00:03 Help me please it's urgent.

you are mixing up between combinatorial conditional syntax and process based one. do not use when inside the process.

i could you plz be more specific ? i used if instead of when but i got this error : Can't infer register for because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[0]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[1]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[2]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[3]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[4]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[5]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[6]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[7]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[8]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[9]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[10]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[11]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[12]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[13]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[14]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[15]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[16]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[17]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[18]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (12152): Can't elaborate user hierarchy "projetppp:inst|brake_var:ppp_inst" Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 20 errors, 7 warnings Error: Peak virtual memory: 371 megabytes Error: Processing ended: Sun May 25 19:59:59 2014 Error: Elapsed time: 00:00:10 Error: Total CPU time (on all processors): 00:00:10 Error (293001): Quartus II Full Compilation was unsuccessful. 22 errors, 7 warnings

you have many other errors e.g. multiple drive on D. you have to be careful as I don't think your brake system will brake

do you have some advices ? because i'm a little bit lost :/ :/ and thank you very much :)

Error (10818): Can't infer register for "D[0]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[1]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[2]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[3]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[4]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[5]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[6]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[7]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[8]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[9]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[10]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[11]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[12]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[13]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[14]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[15]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[16]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[17]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (10818): Can't infer register for "D[18]" at ppp.vhd(47) because it does not hold its value outside the clock edge Error (12152): Can't elaborate user hierarchy "projetppp:inst|brake_var:ppp_inst" Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 20 errors, 6 warnings Error: Peak virtual memory: 371 megabytes Error: Processing ended: Sun May 25 20:16:52 2014 Error: Elapsed time: 00:00:14 Error: Total CPU time (on all processors): 00:00:12 Error (293001): Quartus II Full Compilation was unsuccessful. 22 errors, 6 warnings here is what i got when i changed the code like this : LIBRARY IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use ieee.numeric_std.all; ENTITY brake_var IS port ( clk : in std_logic; reset : in std_logic; chip_select : in std_logic; writedata : in std_logic_vector (31 downto 0); write_n : in std_logic; address : in std_logic; readdata : out std_logic_vector (31 downto 0); out_port1 : out std_logic_vector (7 downto 0); out_port2 : out std_logic_vector (7 downto 0)); END brake_var; ARCHITECTURE brake_system OF brake_var IS signal D : unsigned (31 downto 0); -- distance d'arrÃªt signal v : unsigned (31 downto 0); -- vitesse du vÃ©hicule signal Dmax : unsigned (31 downto 0); -- vitesse max (danger) signal tb : std_logic; signal brake : std_logic; BEGIN readdata <= std_logic_vector(D) when address = '0' else std_logic_vector(v); registers: PROCESS (clk, reset) BEGIN if reset = '0' then D <= (others =>'0'); v <= (others =>'0'); elsif clk'event and clk = '1' then if chip_select ='1' and write_n = '0' then if address = '0' then D (31 downto 0) <= unsigned(writedata (31 downto 0)); else v (15 downto 0) <= unsigned(writedata (15 downto 0)); end if; end if; end if; END PROCESS; distance : PROCESS (clk,reset) begin if reset = '0' then D <= (others =>'0'); elsif clk'event and clk='1' then D(31 downto 0) <= (v(15 downto 0)*3)/10 + (v(15 downto 0)*v(15 downto 0))/100; else D <= (others =>'0'); end if; END PROCESS; tableau_de_bord : PROCESS (clk,reset) begin if reset = '0' then tb <= '0'; elsif clk'event and clk='1' then if D < Dmax then tb <= '0' ; else tb <='1' ; end if ; end if; end process; frein : PROCESS (clk,reset) begin if reset = '0' then brake <= '0'; elsif clk'event and clk='1' then if tb = '0' then brake <= '0'; else brake <='1'; -- freinage end if; end if; END PROCESS; out_port1 <= (others=> tb); out_port2 <= (others=> brake); END brake_system ;

Altera_Forum

Honored Contributor

11 years ago

Error 10500

Hi, i have problems with my vhdl code.

This is the code:

LIBRARY IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

use ieee.numeric_std.all;

ENTITY brake_var IS

port (

clk : in std_logic;

reset : in std_logic;

chip_select : in std_logic;

writedata : in std_logic_vector (31 downto 0);

write_n : in std_logic;

address : in std_logic;

readdata : out std_logic_vector (31 downto 0);

out_port1 : out std_logic_vector (7 downto 0);

out_port2 : out std_logic_vector (7 downto 0));

END brake_var;

ARCHITECTURE brake_system OF brake_var IS

signal D : unsigned (31 downto 0); -- distance d'arrÃªt

signal v : unsigned (31 downto 0); -- vitesse du vÃ©hicule

signal Dmax : unsigned (31 downto 0); -- vitesse max (danger)

signal tb : std_logic;

signal brake : std_logic;

BEGIN

readdata <= std_logic_vector(D) when address = '0' else std_logic_vector(v);

registers: PROCESS (clk, reset)

BEGIN

if reset = '0' then

D <= (others =>'0');

v <= (others =>'0');

elsif clk'event and clk = '1' then

if chip_select ='1' and write_n = '0' then

if address = '0' then

D (31 downto 0) <= unsigned(writedata (31 downto 0));

else v (15 downto 0) <= unsigned(writedata (15 downto 0));

end if;

END PROCESS;

distance : PROCESS (clk,reset)

begin

if reset = '0' then

D <= (others =>'0');

elsif clk'event and clk='1' then

D(31 downto 0) <= (v(15 downto 0)*3)/10 + (v(15 downto 0)*v(15 downto 0))/100;

else

D <= (others =>'0');

end if;

END PROCESS;

tableau_de_bord : PROCESS (clk,reset)

begin

if reset = '0' then

tb <= '0';

elsif clk'event and clk='1' then

tb <= '0' when D < Dmax else

'1' when D > Dmax;

end if;

end process;

frein : PROCESS (clk,reset)

begin

if reset = '0' then

brake <= '0';

elsif clk'event and clk='1' then

brake <= '0' when tb = '0' else

'1' when tb ='1';-- freinage

end if;

END PROCESS;

out_port1 <= (others=> tb);

out_port2 <= (others=> brake);

END brake_system ;

And the error :

Error (10500): VHDL syntax error at ppp.vhd(61) near text "when"; expecting ";"

Error (10500): VHDL syntax error at ppp.vhd(71) near text "when"; expecting ";"

Error: Quartus II 32-bit Analyze Current File was unsuccessful. 2 errors, 0 warnings

Error: Peak virtual memory: 329 megabytes

Error: Processing ended: Sun May 25 19:34:03 2014

Error: Elapsed time: 00:00:03

Error: Total CPU time (on all processors): 00:00:03

Help me please it's urgent.

47 Replies

Altera_Forum
Honored Contributor
11 years ago
and for result type ? it should be 32 ?
Altera_Forum
Honored Contributor
11 years ago
I gave you the widths of each stage
Altera_Forum
Honored Contributor
11 years ago
testing ...
Altera_Forum
Honored Contributor
11 years ago
Critical Warning (332148): Timing requirements not met
same 3 errors persisting ><
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
Critical Warning (332148): Timing requirements not met
same 3 errors persisting ><
--- Quote End ---

what? three multipliers and a tiny bit of logic failing speed.
What device are you using, what speed (I believe it is 50MHz). Even a design done in the kitchen can achieve such speed.
where is your best code.
Altera_Forum
Honored Contributor
11 years ago
Are you sure that the clock in your process is actually the one that you constrained, or driven by a pll connected to the clock you constrained?
If you are using a PLL, what frequency did you define for your design?
Altera_Forum
Honored Contributor
11 years ago
does any one have skype ?
(my pseudo is latrous 92 )
it would be more appropriate to explain to me if it doesnt distrurb :)
thank you for your help

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Error 10500

47 Replies

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