Honored Contributor
Honored Contributorco design of and anti collision system made for cars ;
with D the distance between the object and Dmax is the max tolerable distance v is the car's speed tb is an indicator that indicate is yes or no there is and object and brake is for the abs LIBRARY IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use ieee.numeric_std.all; ENTITY brake_var IS port ( clk : in std_logic; reset : in std_logic; chip_select : in std_logic; writedata : in std_logic_vector (31 downto 0); write_n : in std_logic; address : in std_logic; readdata : out std_logic_vector (31 downto 0); out_port1 : out std_logic_vector (7 downto 0); out_port2 : out std_logic_vector (7 downto 0)); END brake_var; ARCHITECTURE brake_system OF brake_var IS signal D : unsigned (31 downto 0); -- distance d'arrêt signal v : unsigned (31 downto 0); -- vitesse du véhicule signal Dmax : unsigned (31 downto 0); -- vitesse max (danger) signal tb : std_logic; signal brake : std_logic; BEGIN readdata <= std_logic_vector(D) when address = '0' else std_logic_vector(v); registers: PROCESS (clk, reset) BEGIN if reset = '0' then D <= (others =>'0'); v <= (others =>'0'); elsif clk'event and clk = '1' then if chip_select ='1' and write_n = '0' then if address = '0' then D (31 downto 0) <= unsigned(writedata (31 downto 0)); else v (15 downto 0) <= unsigned(writedata (15 downto 0)); end if; end if; end if; END PROCESS; distance : PROCESS (clk,reset) begin if reset = '0' then D <= (others =>'0'); tb <= '0'; brake <= '0'; elsif clk'event and clk='1' then D(31 downto 0) <= (v(15 downto 0)*3)/10 + (v(15 downto 0)*v(15 downto 0))/100; --else --D <= (others =>'0'); if D > Dmax then tb <= '0'; elsif D < Dmax then tb <= '1'; end if; if tb = '0' then brake <= '0'; elsif tb = '1' then brake <= '1'; end if; end if; END PROCESS; out_port1 <= (others=> tb); out_port2 <= (others=> brake); END brake_system ; i putted it all in the same process but i got the same errors :/ :/ i'm more and more confused
