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Altera_Forum's avatar
Altera_Forum
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15 years ago

ERROR 10482 std_ulogic not declared

I write a simple code by VHDL: the top-level: -- USE LIBRARY IEEE 1164 library IEEE; use IEEE.std_logic_1164.all; ------------------------------------------------------------------------ en...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks for your answers!:)

I try to put " library ieee;" and " use ieee.std_logic_1164.all; " before every entities, and compile successed!

I started to learned VHDL recently, there are many different between VHDL and C/C++. In C/C++,it just includ library in the begin of code, but VHDL not. I was confused that did this problem just in QuartusII or in every VHDL compiler?

Anyway, thanks a lot!!