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Altera_Forum's avatar
Altera_Forum
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15 years ago

ERROR 10482 std_ulogic not declared

I write a simple code by VHDL: the top-level: -- USE LIBRARY IEEE 1164 library IEEE; use IEEE.std_logic_1164.all; ------------------------------------------------------------------------ en...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

A VHDL compiler "forgets" about the included libraries between two entities or architectures (I don't remember which one). You must re-include the ieee library and ieee.std_logic_1164.all package before each entity.

It is usually recommended to put only one entity per file.

Is there a reason why you use the unresolved std_ulogic type instead of the more usual std_logic?