Error (10430): VHDL Primary Unit Declaration:already exists in library "work"

Hi all,

in QuartusII web edition, I tried to compile a simple VHDL project and the result is this error message:

error (10430): vhdl primary unit declaration error at clk_div.vhd(56): primary unit "clkdiv" already exists in library "work"

this is my simple project:

 
library IEEE;
use IEEE.std_logic_1164.all;
entity CLKDIV is
    generic
    (
        constant M : integer:=1
    ); -- generic
    port
    (
        reset_i, ref_clk_i, clk_i : in std_logic;
        clk_o, en_o : out std_logic
    ); -- port
end CLKDIV;
architecture CLKDIV_ARCH of CLKDIV is
    signal OutputVal : std_logic;
begin
    MainProcess : process(reset_i, ref_clk_i)
        variable oldClkVal      : std_logic;
        variable nPeriodsCount  : integer range 0 to M-1;
        variable fSync          : boolean;
    begin
        if reset_i='1' then
            oldClkVal:='0';
            nPeriodsCount:=0;
            fSync:=false;
            OutputVal<='0';
            en_o<='0';
        elsif rising_edge(ref_clk_i) then
            en_o<='0';
            if (clk_i/=oldClkVal and fSync) or (clk_i='1' and oldClkVal='0') then
                fSync:=true;
                if nPeriodsCount=0 then
                    if OutputVal='0' then
                        en_o<='1';
                    end if;
                    nPeriodsCount:=M-1;
                    OutputVal<=not OutputVal;
                else
                    nPeriodsCount:=nPeriodsCount-1;
                end if;
            end if;
            oldClkVal:=clk_i;
        end if;    
    end process MainProcess;
 
    clk_o<=OutputVal;
 
end CLKDIV_ARCH;

where am I going wrong?