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RFern19
New Contributor
7 years agoError (10386): VHDL error : non-constant index is always outside the range
Hi folks, I'm using Quartus II standard edition and I'm struggling to run successfully the synthesis of my design. The problem is the following, I have a signal (std_logic_vector type), which is ind...
JOHI
Contributor
7 years agoHello,
I could reproduce your problem and found a possible solution.
You might want to check the indexes, but the basic idea is shown below.
architecture rtl of DE10_STD_FORUM is
constant N_BITS : integer:=8;
-- declare --
signal test_incomingMessage : std_logic_vector (N_BITS-1 downto 0):= (others=> '0');
signal aux_incomingMessage : std_logic_vector ((512*N_BITS)-1 downto 0):= (others=> '0');
begin
-- body --
process (CLOCK2_50)
variable count : integer:= 1;
variable index : natural range 4096 downto 0;
begin
if rising_edge(CLOCK2_50) then
if count < 513 then
index:=count*N_BITS;
aux_incomingMessage(index-1 downto index-N_BITS)<= test_incomingMessage;
count:= count + 1;
end if;
end if;
end process;
end rtl;Best Regards,
Johi.