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Altera_Forum
Honored Contributor
9 years agoError (10349): VHDL Association List error at mult16bit.vhd(41): formal "o" does not
entity mult16bit is generic ( DATA_WIDTH : integer := 16 ); port( a : in std_logic_vector(DATA_WIDTH-2 downto 0); --PARAM b : in std_logic_vector(15 downto 0); ...
Altera_Forum
Honored Contributor
9 years agoI still cannot see the declaration of mult8bit, but I assume the output (c) is 16 bits.
"Left" and "right" are 20 bits, hence the errors. so either: fix the length of left and right only map the appropriate bits.