Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Error (10327): VHDL error at test.vhd(24): can't determine definition of operator "="

Hello everybody,

I am new to vhdl and stuck on an error message :

Error (10327): VHDL error at test.vhd(24): can't determine definition of operator ""="" -- found 0 possible definitions

I used :

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

and declared:

port (Q : in signed(3 downto 0));

....

variable Q_1 : unsigned(0 downto 0);

... here is the line of code that have the error

if (q(0)="0" and q_1="1") then

...

Thank you for your time.

Regards.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    well you better tell us what you want to do with Q and Q_1.

    you can just say:

    Q_1(0) := Q(0);

    --- Quote End ---

    sorry for not making it clear. what i wanted to do was to assign the 0th index of Q to Q_1.

    Q_1:= Q(0);

    thank you for your time :)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I mean what actually you are trying to do in your module in general.

    Regarding your errors you need to assign same type on either side of =

    a single bit is of value (0 or 1)and can be assigned to any other single bits. So are multiple grouped bits. But a bus need to be same type e.g. std_logic_vector or signed or unsigned on either side of = or use cast like:

    data_signed <= signed(data_std_logic);
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Try using single quotes(') instead of double quotes (") around the values you're testing against. ' is for characters, " is for strings.