Error (10327): VHDL error at test.vhd(24): can't determine definition of operator "="

I mean what actually you are trying to do in your module in general.

Regarding your errors you need to assign same type on either side of =

a single bit is of value (0 or 1)and can be assigned to any other single bits. So are multiple grouped bits. But a bus need to be same type e.g. std_logic_vector or signed or unsigned on either side of = or use cast like:

data_signed <= signed(data_std_logic);