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Altera_Forum
Honored Contributor
Honored Contributorerror 10161 when importing vhdl packages to system verilog
Hi, My toplevel design is in system verilog, I import a VHDL package with record type, quartus errors with "Error (10161): Verilog HDL error at dummy_sysver.sv(3): object "dummy_vhd_pkg" is not...
Altera_ForumHonored Contributor
Honored ContributorI would raise a case with Altera MySupport. Their SV support isnt full, and other vendors (cadence in particular) have a terrible time importing records from VHDL in to SV, so this isnt just a Quartus problem.
For reference: Modelsim also has a problem with VHDL record that contain arrays that have 0 length, but this is more a System verilog limitation Cadence cannot import any records that contain types other than std_logic or std_logic_vector, and nested records are also not possible.
