Error 10028, 10029 Verilog

Thank you, yeah that makes sense. My big problem is trying to change between the first set of states to the second set of states.

At the moment, I'm thinking of breaking the 2 separate triggers into a single trigger before I ever hit that module so I don't get that error. I'll be using a clock signal that changes every second and a pushbutton that goes when I tell it to. I need to input 10 numbers into the other code so I want the pushbutton to have priority for the first 10 cycles, then the clock can take over.

I've created a separate module to accommodate this but now I don't understand why my outputs are always stuck at VCC.

The code below should:

Take 2 inputs, when sw_in is triggered my count variable will go up by one and it will output the sw_in to sw_out. Once count reaches 2'd10 it will let clk_out become clk_in.

module counter(clk_in,sw_in,clk_out,sw_out);
input clk_in,sw_in;
output reg clk_out,sw_out;
reg  count;
initial begin
count = 2'd00;
end // end initial
always (AT) (posedge sw_in or posedge clk_in) begin
if (sw_in) begin
    count <= count + 2'd01;
    sw_out <= sw_in;
end // end if 1
if (clk_in) begin
    if (count >= 2'd10) begin
        clk_out <= clk_in;
    end
end // end if 2
    
end // end always
endmodule

Do I need to reset the sw_out and clk_out to 0 after they pass through?