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Altera_Forum's avatar
Altera_Forum
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11 years ago

erreur VHDL

Hello! In fact,i have a small problem but I don't understand what I should do here is my code: library ieee ;use ieee.std_logic_1164.all ; use ieee.std_logic_signed .all ; entity M...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi,

There are quite a few errors in that piece of code that you should think about first.

To give a hint on the specific question, have you considered the width of the two signals you are doing xor on?

Cheers