EPCS Flash Access on DE0 Nano (Qsys)

Hello,

I'm having trouble accessing the EPCS Flash on a new DE0 Nano board. I've set up a Nios II system in Qsys and included the EPCS Serial Flash Controller. (Other system components include the UP Clock Signals for SDRAM Clock, SDRAM Controller, Sys ID, JTAG UART, and Interval Timer). At this point I'm just trying to make sure I can communicate with the flash using the nios2-flash-programmer (with --epcs and --debug flags). The EPCS reset is connected to both the clk_reset (reset output from clock source) and jtag_debug_module_reset from Nios II; the epcs_control_port is connected to both data master and instruction master ports on the Nios II CPU. I've tried setting CPU reset & exception vectors to either SDRAM (this allows the processor to run & code to execute, but no flash access), or to EPCS (which results in the Nios Console view in Eclipse not loading, and the program fails to launch).

The board does have the newer 64Mbit flash chip, and I've included the override file with an entry for [EPCS-010216]. I am specifying the base address as given in the address map in Qsys. I have modified the pin settings for DATA[0], DCLK, DATA[1]/ASDO, and FLASH_nCE/NCSO as regular I/O (as instructed in the Embedded Peripherals Guide for EPCS Serial Flash Controller Core). I have also exported the EPCS conduit to the top level and assigned the appropriate pins in the pin planner.

The exact output is as follows:

$ nios2-flash-programmer --epcs --debug --base=0x4001000 --verbose
Reading override file "C:/altera/12.1sp1/nios2eds/bin/nios2-flash-override.txt"
Using cable "USB-Blaster ", device 1, instance 0x00
Resetting and pausing target processor: OK
Processor data bus width is 32 bits
Looking for EPCS registers at address 0x04001000 (with 32bit alignment)
  Initial values: 0001703A 04C00074 9801483A 9CFFF804 983FFD1E 0000203A
  Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x04001100 (with 32bit alignment)
  Initial values: 93000237 6300080C 603FFD26 90000335 A8000C26 03010004
  Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x04001200 (with 32bit alignment)
  Initial values: 4A40100C 483FFD26 92C00135 92400237 4A40200C 483FFD26
  Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x04001300 (with 32bit alignment)
  Initial values: 00000000 00000000 00000000 00000000 00000000 00000000
  Not here: SPI_SLAVE_SEL has 0 valid bits (should be between 1 and 16)
Looking for EPCS registers at address 0x04001400 (with 32bit alignment)
  Initial values: 00000000 00000000 00000260 00000000 00000000 00000001
  Valid registers found
EPCS signature is 0x00
EPCS identifier is 0x000000
No EPCS layout data - looking for section 
Unable to use EPCS device
Leaving target processor paused

I've tried with the tools in Quartus 11 Subscription Edition, 12.0 Web Edition, and 12.1 Web Edition, so I assume it's not a tool version problem. I am running these on Win7 x64 SP1.

I'm porting this from a design on the DE0 (cyclone III) that ran fine (but used a CFI flash). Eventually I'd like to store the FPGA configuration, the C code, and some static lookup tables in the left over room. For now I'd just like to be able to ensure communication is working.

I've tried most if not all the troubleshooting steps in the other similar posts. I'm sure I'm missing something simple here. Any ideas?

Thank you in advance!