If you're using the NIOS processor, you basically write a AVALON slave device with the memory mapped registers you require, then instantiate it with exported signals that directly drive the FIR you designed.
If you are using some external CPU, then you would have to do the same thing, except it would more likely be an EMIF, AMBA, or some other interface.
The Avalon bus is fairly strait forward and can be found here:
www.altera.com/literature/manual/mnl_avalon_spec.pdf SOPC Builder has a wizard that allows will read this slave device verilog, and assign the AVALON and non-avalon signals. For signals that would be directly connected to your FIR, you would assign these as EXPORT, and they will show up in the top level of the design. This is where you would instantiate the FIR filter as well, manually assign the ports.
If you want the data path for the FIR to come from and go to system memory, and not just the setup, you probably want a both a Avalon Master and and Avalon Slave device that hooks it up.
Here it's a little more complex, and but basically the same idea. If you ware writing a master device however, be careful on memory boundaries if using bursting. The Avalon bus doesn't currently recognize memory burst boundaries, and will give you out of order data in some cases.
Pete
Honored Contributor
