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Altera_Forum's avatar
Altera_Forum
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11 years ago

Effective leakage estimate on Stratix V

Hi

I have a question regarding leakage estimate in Quartus.

I write a design and map it in Quartus onto Stratix V. However, a particular design usually takes only a portion resource of the whole board, and I want to find the leakage which comes from this used portion. There is only one value "core static power" reported in PowerPlay. So my thought is to look at floorplan map in "Chip Planner", and calculate how many percent of the board is used. Then multiply this percentage by core static power value. Is this method OK? Is there any better idea to do this estimation?

Thanks.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    My understanding is the static power value applies to the whole device. It might be rather difficult to estimate the leakage for a specific portion of logic used since different core blocks might contribute to different % of the static powerl. However, just for rought estimation, I believe there is no harm using your existing method.