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Altera_Forum's avatar
Altera_Forum
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9 years ago

Edge detection asynchronous signal fails

Hello, I am working on a fairly simple VHDL design where I am trying to detect the rising_edge of an input. Whenever a rising_edge is detected I want to multiply another input by 2 and output ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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I don't know whether it is the code or the post place & netlist. I am running a Gate Level Simulation. I am using Quartus II.

Thanks for your tip with the time delays!

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Qate level simulation is the quartus compiled code you are simulating. You are not simulating your RTL directly.